1. Field of the Invention
The present invention relates to a decoder arranged to generate N output signals from two or more precharged input signals.
2. Description of the Prior Art
It is often necessary to provide decoder circuits for producing a number of output signals based on two or more precharged input signals. The output signals generated by the decoder circuit may, for example, be used as input signals to domino logic. During the precharge phase, it is typically required that all of the output signals from the decoder are at the same logic value, and that during the subsequent evaluate phase, one of the output signals transitions to another logic value. For example, if a decoder circuit is to produce outputs suitable for use with a CMOS domino logic wired NOR gate, then the required behaviour is that during the precharge phase all of the outputs of the decoder are at a logic 0 level, and that during the subsequent evaluate phase exactly one output makes a single transition from a logic zero to a logic 1 value. It is also necessary to ensure that all of the output signals from the decoder circuit are valid after the single transition of one of the outputs has taken place.
For decoder circuits using precharged inputs, the above behaviour is that of a decoder implemented using an AND gate structure to produce the outputs. Considering the example of an N bit encoded input, this requires an N-input AND gate per output. An N-input AND gate requires either an N stack of n-type transistors, or an equivalent cascade of AND gates in series. However, as the number of inputs increases, an AND based decoder circuit becomes slower with the increased number of stacked or cascaded devices.
Accordingly, it is an object of the present invention to provide an improved decoder which during the precharge phase produces all of the outputs at the same logic value, and during a subsequent evaluate phase causes one of the output signals to make a transition to another logic value, whilst ensuring that all of the output signals are valid once that output signal has transitioned.